The Truth Table of the JK Flip Flop is shown below. When both J and K are at logic “1”, the JK Flip Flop toggle. Similarly, the input K is inhibited by 0 status of Q through the upper NAND gate in the “RESET” condition. If the circuit is in the “SET” condition, the J input is inhibited by the status 0 of Q through the lower NAND gate. This cross-coupling of the RS Flip-Flop is used to produce toggle action. The two-input AND gates of the RS flip-flop is replaced by the two 3 inputs NAND gates with the third input of each gate connected to the outputs at Q and Ǭ. The S and R inputs of the RS bistable have been replaced by the two inputs called the J and K input respectively. The circuit diagram of the JK Flip Flop is shown in the figure below: The four inputs are “logic 1”, ‘logic 0”. The JK Flip Flop has four possible input combinations because of the addition of the clocked input. Thus, to prevent this invalid condition, a clock circuit is introduced.

When both the inputs S and R are equal to logic “1”, the invalid condition takes place. The JK Flip Flop is basically a gated RS flip flop with the addition of the clock input circuitry. Thus to overcome these two problems of the RS Flip-Flop, the JK Flip Flop was designed.

Secondly, if the state of S or R changes its state while the input which is enabled is high, the correct latching action does not occur.

Firstly, the condition when S = 0 and R = 0 should be avoided.The basic NAND gate RS flip-flop suffers from two main problems. The basic symbol of the JK Flip Flop is shown below: The JK Flip Flop name has been kept on the inventor name of the circuit known as Jack Kilby. The difference is that the JK Flip Flop does not the invalid input states of the RS Latch (when S and R are both 1).

Jk flip flop multisim